Non-transparent sharing of return predictor targets between contexts in some Intel(R) Processors may allow an authorized user to potentiall…
Non-transparent sharing of return predictor targets between contexts in some Intel(R) Processors may allow an authorized user to potentially enable information disclosure via local access.
Hardware structures shared across execution contexts (e.g., caches and branch predictors) can violate the expected architecture isolation between contexts.
https://cwe.mitre.org/data/definitions/1303.html →Open in CWE collection →An adversary exploits a hardware design flaw in a CPU implementation of transient instruction execution to expose sensitive data and bypass/subvert access control over restricted resources. Typically, the adversary conducts a covert channel attack to target non-discarded microarchitectural changes caused by transient executions such as speculative execution, branch prediction, instruction pipelining, and/or out-of-order execution. The transient execution results in a series of instructions (gadgets) which construct covert channel and access/transfer the secret data.
https://capec.mitre.org/data/definitions/663.html →Open in CAPEC collection →| Product | Vendor | Status |
|---|---|---|
| intel-microcode | Tracked | |
| intel-microcode | Tracked | |
| intel-microcode | Tracked | |
| intel-microcode | Tracked | |
| intel-microcode | Tracked | |
| intel-microcode | Tracked | |
| intel-microcode | Tracked | |
| intel-microcode | Tracked | |
| intel-microcode | Tracked | |
| intel-microcode | Tracked | |
| intel-microcode | Tracked | |
| microcode_ctl | Tracked |