Hardware logic with insecure de-synchronization in Intel(R) DSA and Intel(R) IAA for some Intel(R) 4th or 5th generation Xeon(R) processors…
Hardware logic with insecure de-synchronization in Intel(R) DSA and Intel(R) IAA for some Intel(R) 4th or 5th generation Xeon(R) processors may allow an authorized user to potentially enable escalation of privilege local access
The hardware logic for error handling and security checks can incorrectly forward data before the security check is complete.
https://cwe.mitre.org/data/definitions/1264.html →Open in CWE collection →An adversary exploits a weakness enabling them to elevate their privilege and perform an action that they are not supposed to be authorized to perform.
https://capec.mitre.org/data/definitions/233.html →Open in CAPEC collection →An adversary exploits a hardware design flaw in a CPU implementation of transient instruction execution to expose sensitive data and bypass/subvert access control over restricted resources. Typically, the adversary conducts a covert channel attack to target non-discarded microarchitectural changes caused by transient executions such as speculative execution, branch prediction, instruction pipelining, and/or out-of-order execution. The transient execution results in a series of instructions (gadgets) which construct covert channel and access/transfer the secret data.
https://capec.mitre.org/data/definitions/663.html →Open in CAPEC collection →| Product | Vendor | Status |
|---|---|---|
| kernel | Tracked | |
| kernel | Tracked | |
| kernel | Tracked | |
| kernel | Tracked | |
| kernel | Tracked | |
| kernel | Tracked | |
| kernel | Tracked | |
| kernel | Tracked | |
| kernel | Tracked | |
| kernel | Tracked | |
| kernel | Tracked | |
| kernel | Tracked | |
| kernel-rt | Tracked | |
| kernel-rt | Tracked | |
| kernel-rt | Tracked | |
| kernel-rt | Tracked | |
| linux | Tracked | |
| linux | Tracked | |
| linux | Tracked | |
| linux | Tracked |